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Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits

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2 Author(s)
Mukhopadhyay, S. ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K.

In this work we have developed an accurate model of total leakage in a transistor stack based on the compact model of gate, subthreshold and band-to-band-tunneling leakage. Using this model, we have analyzed the opportunities for overall stand-by leakage reduction in scaled devices using transistor stacking and proved that the best input vector that minimize overall leakage depends on the relative magnitude of the different leakage components. A novel stacking technique based on the ratio of the different leakage components is proposed and its effectiveness in total leakage reduction in transistor stack and logic gate is analyzed.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003