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3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

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11 Author(s)
Jonghae Kim ; Semicond. Res. & Dev. Center, IBM, Hopewell Junction, NY, USA ; Plouchart, J.-O. ; Zamdmer, N. ; Sherony, M.
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This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 μm SOI CMOS technology. An effective capacitance density of 1.76 fF/μm2 is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

Published in:
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference: 12-14 June 2003

Page(s):
29 - 32
Print ISBN:
4-89114-034-8
INSPEC Accession Number:
7869109
Digital Object Identifier :
10.1109/VLSIC.2003.1221153
Product Type:
Conference Publications

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