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A post-silicon clock timing adjustment using genetic algorithms

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4 Author(s)
Takahashi, E. ; Adv. Semicond. Res. Center, AIST, Tsukuba, Japan ; Kasai, Y. ; Murakawa, M. ; Higuchi, T.

A post-silicon clock timing adjustment architecture utilizing genetic algorithms (GA) is proposed, which has three advantages: (1) enhanced clock frequency leading to improved operating yields, (2) lower power supply voltages while maintaining operating yield, and (3) reductions in design times. Experiments with two different developed LSI chips and a design experiment demonstrated these advantages with a clock frequency enhancement of 25% (max), a power supply voltage reduction of 33%, and 21% shorter design times.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003