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Hybrid hierarchical timing closure methodology for a high performance and low power DSP

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2 Author(s)
K. Shi ; Professional Services, Synopsis Inc., Dallas, TX, USA ; G. Godwin

A hybrid hierarchical timing closure methodology has been developed to combine strength of the subchip based hierarchical timing closure method and flat design based logic-physical combined optimization method for a 1.5 million gates, high performance and ultra-low power DSP which has been used in a number of wireless applications. The principle and the implementation details of the methodology are provided.

Published in:

Design Automation Conference, 2003. Proceedings

Date of Conference:

2-6 June 2003