Referenced Items are not available for this document.
This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:11
,
Issue:
3
)
Date of Publication: June 2003
- Page(s):
- 511 - 514
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 7720142
- Digital Object Identifier :
- 10.1109/TVLSI.2003.812322
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 04 August 2003
- Issue Date :
- June 2003
- Sponsored by :
- IEEE Circuits and Systems Society
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