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Gbit/s lossless data compression hardware

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2 Author(s)
Nunez, J.L. ; Dept. of Eng. & Design, Univ. of Bath, UK ; Jones, S.

This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 3 )