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Analysis of bit transition count for EDAC encoded FSM

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4 Author(s)
Venkateswaran, N. ; Waran Res. Found., Chennai, India ; Balaji, V. ; Mahalingam, V. ; Rajaprabhu, T.L.

The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.

Published in:

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Date of Conference:

7-9 July 2003

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