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Fault injection in digital logic circuits at the VHDL level

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2 Author(s)
Seward, S.R. ; Comput. Sci. & Comput. Eng. Dept., Arkansas Univ., Fayetteville, AR, USA ; Lala, P.K.

This paper presents hardware-based techniques for transient and permanent fault injection in VHDL descriptors of both combinational and sequential digital circuits. The designer can choose the fault injection rate, which may vary from 100% (permanent fault) down to 0.01% (transient fault).

Published in:

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Date of Conference:

7-9 July 2003