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We examine a low-cost, zero-latency, non-intrusive CED method for restricted error models. The method is based on compaction of the circuit outputs, prediction of the compacted responses, and comparison. This method also achieves significant hardware cost reduction by utilizing the information available through the restricted error model. We assume that the error model is not defined through permanent or transient faults in the hardware, but rather in terms of the erroneous behavior that such faults induce. Thus, any fault model can be described by providing for every input combination the error-free response and all erroneous responses resulting from faults in the model.