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Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC

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2 Author(s)
Yi Shao ; Electr. & Comput. Eng. Dept., California Univ., San Diego, CA, USA ; S. Dey

This paper addresses the soft-error problem in UDSM circuits by presenting on-line fault-tolerant circuit design techniques. In our scheme, separate dual transistor (SDT) structure is introduced into the register design as a key component to increase the input-signal stability as well as the robustness of the circuit against the effects of ionizing particles. Our work not only demonstrates the feasibility of its physical implementation, but also shows the cost effectiveness. To compare with other fault-tolerant techniques, ISCAS89 circuits have been synthesized with the SDT standard cells to investigate its cost/timing overheads. Our benchmark comparison reveals its better applicability over two representative techniques (TMR and ECC) for the logic circuits in digital systems.

Published in:

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Date of Conference:

7-9 July 2003