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Stress distribution on [100] Si wafer mapped by novel I-V analysis of MOS tunneling diodes

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2 Author(s)
Chao-Chi Hong ; Dept. of Electr. Eng, Nat. Taiwan Univ., Taipei, Taiwan ; Jenn-Gwo Hwu

The current-voltage (I-V) characteristics of metal-oxide-semiconductor tunneling diodes distributed over a 3-in Si wafer were analyzed to investigate the stress distribution on the wafer. Generally, the substrate injection saturation current (J/sub sat/) decreases as the gate injection leakage current (J/sub g/) increases, the latter being dominated by oxide thickness via a trap related mechanism. A universal curve to fit all analyzed data was found and it is suggested that devices with extremely high (low) J/sub sat/ at a given J/sub g/ should be located in areas of the silicon lattice with relatively high external compressive (tensile) stress because of the stress-induced bandgap variation effect. The mapped locations of the highly stressed devices on a 3-in [100] Si wafer correspond to the patterns of slips caused by thermal stress during rapid thermal processing, as described in previous reports.

Published in:

IEEE Electron Device Letters  (Volume:24 ,  Issue: 6 )