By Topic

The detection of defects in a niobium tri-layer process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. A. Joseph ; Testable Design & Testing of Microsystems Group, Univ. of Twente, Enschede, Netherlands ; S. Heuvelmans ; G. J. Gerritsma ; H. G. Kerkhoff

Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:13 ,  Issue: 2 )