Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
8 Author(s)
Jagannathan, B. ; IBM Microelectron. Semicond. R&D Center, Hopewell Junction, NY, USA ; Meghelli, M. ; Chan, K. ; Jae-Sung Rieh
more authors

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay.

Published in:

Electron Device Letters, IEEE  (Volume:24 ,  Issue: 5 )