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A slew-rate controlled output driver using PLL as compensation circuit

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5 Author(s)
Soon-Kyun Shin ; Mixed Signal Core Group, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea ; Seok-Min Jung ; Jin-Ho Seo ; Myeong-Lyong Ko
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A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-μm CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 7 )

Date of Publication:

July 2003

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