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A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm

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3 Author(s)
Soonhak Kwon ; Dept. of Math., Sungkyunkwan Univ., Suwon, South Korea ; Chang Hoon Kim ; Chun Pyo Hong

By using a polynomial basis with LSB (Least Significant Bit) first scheme, we present new bit serial and bit parallel systolic multipliers over GF(2m). Our bit serial systolic multiplier has only one control signal with 10 latches in each basic cell. Also, our bit parallel multiplier has unidirectional data flow with 7 latches in each basic cell. Thus, whether it is bit serial or bit parallel, our multiplier has a better or comparable hardware complexity and critical path delay and has the same unidirectional data flow to the multipliers with MSB (Most Significant Bit) first scheme.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003