Referenced Items are not available for this document.
In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the space between the dies (scribe lines) on the wafers. The test structure has been implemented in a standard 0.18-μm digital CMOS technology.
Published in:
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
(Volume:5
)
Date of Conference: 25-28 May 2003
- Page(s):
- V-569 - V-572 vol.5
- Print ISBN:
- 0-7803-7761-3
- INSPEC Accession Number:
- 7762859
- Digital Object Identifier :
- 10.1109/ISCAS.2003.1206376
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
