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A modular test structure for CMOS mismatch characterization

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7 Author(s)
M. Conti ; Dipt. di Elettronica ed Automatica, Universita Politecnica delle Marche, Ancona, Italy ; P. Crippa ; F. Fedecostante ; S. Orcioni
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In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the space between the dies (scribe lines) on the wafers. The test structure has been implemented in a standard 0.18-μm digital CMOS technology.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003