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In this paper, we introduce a tile-graph-based approach to power planning. For a given floorplan solution, the power inputs are modeled into a tile graph, the minimum capacity of each power input and the maximum power need of each module in a floorplan are accumulated in an associated tile. An efficient cost evaluation algorithm is adopted to calculate the cost of power planning. As its computation time is quite short, it is reasonable to integrate such an algorithm into an iterative floorplanning environment.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:5 )
Date of Conference: 25-28 May 2003