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Exploiting reconfigurability for low-power control of embedded processors

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5 Author(s)

This paper proposes and evaluates a new implementation for the lowest level of instruction cache memories, which provides considerable power savings in the control memory subsystem of standard embedded processors. Instead of using power-demanding 6-T SRAMs for small I-caches, we exploit the possibility of using smaller switching capacitances, substituting the memory array with a specialized programmable logic circuit. Switching gains provided by this substitution are presented, illustrating a dramatic potential for power reduction in processor architectures for portable multimedia embedded applications.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003