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The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals the overall core architecture (and the architecture of its constituent components such as arithmetic unit, controller, and memory) required in order to employ the algorithm such that power is reduced and the overheads are minimised. In order to study the effect of the algorithm on power consumption both two's complement and sign magnitude number representations have been investigated. Results have been provided and compared to a conventional FIR filtering core demonstrating overall power reduction of up to 49% with less than 5% increase in area.