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A very low-power 8-bit ΣΔ converter in a 0.8 μm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V

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2 Author(s)
Gerosa, A. ; Dept. of Inf. Eng., Padova Univ., Italy ; Neviani, A.

This work presents a ΣΔ analog-to-digital converter intended for the sensing stage of a cardiac pacemaker. The realized circuit is a practical example of how design techniques devoted to the realization of integrated circuits operating in low-voltage and low-power environment, can benefit a specific application. Particularly the integration of critical blocks of a pacemaker in a sub-micron technology allows to reduce the implantable device size and its power consumption. The ΣΔ converter has been integrated in a 0.8 μm CMOS technology and dissipates less than 2.2 μW when operated at 1.8 V. According to measurement results, the converter has a DR larger than 50 dB, and has an accuracy of 8-bit with DNL and INL both within ±half LSB. The chip area is below 1 min.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003