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Next-generation bionic ears or cochlear implants will be fully implanted inside the body of the patient and consequently have very stringent requirements on the power consumption used for signal processing. We describe a low-power programmable analog VLSI processing channel that implements bandpass filtering, envelope detection, logarithmic mapping and analog-to-digital conversion. A bionic ear processor may be implemented through the use of several such parallel channels. In a proof-of-concept 1.5 μm AMI MOSIS implementation, the most power-hungry channel of our system (7.5 kHz center frequency) consumed 7.8 μW of power, had an internal dynamic range (IDR) of 51 dB, and provided 64 discriminable levels of loudness per channel. Such numbers already satisfy the requirements of today's commercial bionic ear processors and can lower the power consumption of even advanced DSP processing schemes of the future by an order of magnitude. Our processing channel is also well suited for use in low power speech recognition front ends, which commonly require the same sequence of operations in cepstrum-like front ends. Future improvements in the interfaces between the various stages of our processing channel, which were not optimized in this implementation, promise a potential internal dynamic range of more than 60 dB with little or no increase in power.