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Advances in FPGA technology and in design automation tools have changed the way digital electronics are created. Shematic entry of gates is becoming deprecated by hardware description languages (HDLs) and sophisticated synthesis tools. This requires that the designer have a complete understanding of the entire design flow so that they can utilize the efficiency of HDLs while thinking about the hardware that will be created. This paper reviews three years worth of experience in teaching a two-semester senior/graduate course sequence on Hardware Design Methodologies using the Mentor Graphic's HDL Designer series tools and targeting FPGAs. Currently, all project use an ARM-embedded FPGA as their target. Given the complexity of these new devices, the tools, and only two semesters, we discuss the potential, the limitations/difficulties and the general sanity of this approach.