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Stochastic logic, also known as stochastic computing, provides very low computation hardware area, fault tolerance, and efficient hardware implementations for high clock rates. It has long been defined as the processing of signals encoded as Bernoulli random sequences. This assumed definition has created its most notable restriction: the requirement to sample much faster than the Nyquist rate, severely limiting the allowable signal bandwidth. We demonstrate that stochastic logic can be extended beyond Bernoulli sequences to include binomial (N, p) representations where N > 1. By expanding the definition of stochastic computing we create a new design methodology that enables the engineer to obtain greater signal bandwidth by increasing the circuit size.