Referenced Items are not available for this document.
The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of /spl sim/100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.
Published in:
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
(Volume:2
)
Date of Conference: 3-6 Nov. 2002
- Page(s):
- 1064 - 1068 vol.2
- ISSN :
- 1058-6393
- Print ISBN:
- 0-7803-7576-9
- INSPEC Accession Number:
- 7792654
- Conference Location :
- Pacific Grove, CA, USA
- Digital Object Identifier :
- 10.1109/ACSSC.2002.1196947
- Product Type:
- Conference Publications
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