Skip to Main Content
The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of /spl sim/100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on (Volume:2 )
Date of Conference: 3-6 Nov. 2002