By Topic

Transmit and receive digital filters subject to hardware cost constraints

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fox, T.W. ; Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada ; Carreira, A. ; Turner, L.E.

A method for the design of field programmable gate array (FPGA) based bit-serial Finite duration impulse response (FIR) transmit and receive digital filters is presented. Transmit and receive digital filters can be designed with near zero inter-symbol interference (ISI) and a specified normalized minimum stopband attenuation while using a specified number of logic elements (LEs). A tradeoff between the ISI and the hardware cost (the number of required LEs) is explored. It is shown that it is possible to obtain low cost transmit and receive digital filters at the expense of higher ISI.

Published in:

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on  (Volume:2 )

Date of Conference:

3-6 Nov. 2002