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P3A: a partitionable parallel/pipeline architecture for real-time image processing

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5 Author(s)
Gray, C.T. ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; Liu, Wentai ; Hughes, T. ; Cavin, R.
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A high-performance partitionable parallel/pipeline architecture (P 3A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P3A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining

Published in:

Pattern Recognition, 1990. Proceedings., 10th International Conference on  (Volume:ii )

Date of Conference:

16-21 Jun 1990