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This paper presents a high-level hardware description environment based on the logic programming language Prolog, called HIDE. The latter has been designed in an attempt to address the problem of abstract hardware design and hardware efficiency. HIDE provides more abstract hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. It enables highly scaleable and parameterised composition of blocks using a small set of constructors (e.g. horizontal, vertical composition), and generates pre-placed configurations in EDIF format for Xilinx Virtex FPGAs. The paper presents the syntax and semantics of HIDE and illustrates its use in the construction of a bit parallel multiplier core for Xilinx Virtex FPGAs.
Date of Conference: 16-18 Dec. 2002