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In this paper, two novel methods for current regulation are proposed. Both methods follow the synchronized on-off principle. In the classical approach, transistors are switched depending on the sign of the current error, which in turn is sampled at equal time intervals. In the first method, the current vector at the end of the interval is predicted for two possible cases when either the active voltage vector pointing toward current error or the zero voltage vector is applied. The one producing the smaller current error at the end of the sampling interval is chosen, thus obtaining drastic reduction of the switching frequency. In the second method, the best fitting active voltage vector succeeds the zero vector during the same time interval. A simple algorithm is used to calculate the duty cycle thus gaining the smallest possible current error. The method is compared with the CRPWM. Both methods were simulated and tested on a laboratory model with passive load. In the last part of the paper, the behavior of the second method is tested for erroneously estimated load parameters. The two methods show very small degradation of performance even when a rather high parameter error is introduced.