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The main source of power dissipation for dynamic CMOS circuits is due to charging and discharging of intrinsic capacitances, commonly referred to as switching power. As switching power dissipation is proportional to the square of supply voltage, lowering the supply voltage is the most effective way to reduce switching power dissipation. However, the reduction of switching power by lowering the supply voltage takes place at the cost of performance. In order to maintain the performance, it is necessary to scale down the threshold voltage. But, as the threshold voltage is scaled down, the subthreshold leakage current increases dramatically, leading to a large increase in leakage power dissipation. Recent research has revealed that with the gradual shrinking of device sizes, the leakage power dissipation is becoming more and more dominant, and it is likely to become comparable to switching power dissipation in future generation VLSI circuits. This has motivated us to develop suitable techniques for the reduction of leakage power dissipation in dynamic CMOS circuits, a problem which has not been addressed by any researcher. This paper proposes a technique for containing the leakage power using two threshold voltages (dual-VT) in the realization of circuits. Necessary care has been taken such that the dual-VT dynamic circuits can be kept in standby mode and dissipate small leakage power. Substantial reduction in leakage power has been demonstrated without compromise in performance for both domino and nora style of realizations.