By Topic

The impact of bit-line coupling and ground bounce on CMOS SRAM performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Li Ding ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Mazumder, P.

In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those noises impair the performance of SRAM. The impact of noises is expressed in term of a coupling noise degradation factor and a ground bounce degradation factor. We have used analytical techniques to reduce the governing nonlinear ordinary differential equations to some manageable form and have derived very simple formulas for those degradation factors. Experiments have shown that the results obtained using the derived simple formulas are in good agreement with HSPICE simulation.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003