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We describe a set of techniques for representing the high-level behavior of a digital subsystem as a collection of nondeterministic finite automata, NFA. Desired behavioral dynamics such as functional dependencies, sequential timing, and sequencing, and control state are similarly modeled. Using techniques similar to that used in formal model checking, we implicitly explore the possible execution sequences of the system, obeying all imposed constraints. This provides a very general, systematic mechanism for performing high-level synthesis of cyclic, control dominated behaviors, constrained by arbitrary sequential constraints. In this paper, we show that these techniques are scalable to practical problem sizes and complexities by constructing a high-level model of a (MIPS IV) RISC microprocessor and then performing exact scheduling and related design tradeoffs on this model. The model is constructed at the level of register transactions to address the majority of contention and arbitration issues of architectural interest.