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A VLSI digital filter bank

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2 Author(s)
M. Yuschik ; University of South Carolina, Columbia, South Carolina ; H. Kobayashi

This paper investigates architectures for digital signal processors (DSP's). Typical DSP's are examined to identify their computation and communication requirements. By decomposing the general filtering function into primitive second-order digital recursive filter (2DRF) modules, an architecture is developed which contains the basic operations of every signal processor. This leads to the design of a novel, programmable arithmetic unit for high speed sum-of-product (SOP) computation which possesses hardware speed and software flexibility. For spectral decomposition of speech, a number of DRF modules must operate simultaneously. A set of MC68000 microcomputers is used to identify the interprocessor communication requirements for modules acting as a digital filter bank (DFB). A versatile bus structure permits the investigation of various data transfer and control strategies for different systems. This leads to the design of a VLSI DFB for real-time speech processing.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '84.  (Volume:9 )

Date of Conference:

Mar 1984