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Algorithm and a new processor architecture for computing the DFT

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1 Author(s)
Arambepola, B. ; GEC Research Laboratories, Middlesex, UK

A new architecture for a DFT processor, based on the prime factor algorithm (PFA) is proposed. This processor offers very high throughput rates and is well matched to present LSI implementation capabilities. A new indexing scheme for the PFA is also presented, which results in an in-place and in-order flexible algorithm.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '83.  (Volume:8 )

Date of Conference:

Apr 1983