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The architecture of a signal processor developed through simulation

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3 Author(s)
M. Carapic ; "Boris Kidric", Belgrade, Yugoslavia ; Z. Jovanovic ; Z. Mihajlovic

Host machines of signal processors are closely related to algorithm characteristics, and therefore simultaneous development of architecture and micro-programs could be succesfully done through simulation. In the created simulator, the program modules correspond to hard-ware components, and they are activated only once during a microcycle by using an "Equivalent generalized pipeline stage" model. The architecture is briefly described, with more significance paid to the address generation.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '82.  (Volume:7 )

Date of Conference:

May 1982