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Digital phase locked loop

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2 Author(s)
C. Reddy ; California State University, Fullerton, California ; E. Fountain

This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input. The Oscillator consists of a cascade of decade rate Multipliers. The output frequency is numerically controlled using binary words instead of voltage. The input word to the Oscillator determines accurately the input frequency in a locked loop.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '78.  (Volume:3 )

Date of Conference:

Apr 1978