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A PE (Processing Element) LSI for a DTW (Dynamic Time Warping) linear array processor has been designed. In designing this LSI, major effort has been focused on achieving regular data-flow among adjacent PEs maintaining pipelined operation in the array. A three data channel structure, a triple buffer structure and sophisticated control schemes make it possible for the designed LSI to carry out MIMD (Multiple Instruction and Multiple Data streams) and continuous pipelined DTW processing in sync with regular pattern input. Due to the high speed real time operation, and the versatile function of this PE-LSI, a high performance linear array processor can be constructed using a small number of PEs. The high speed operation of LSI is pursuited to achieve real time processing. Continuous speech recognition with an approximate vocabulary of 1000 words can be achieved using only 20 to 30 of these PE-LSIs.
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87. (Volume:12 )
Date of Conference: Apr 1987