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A CCITT standard 32 kbps ADPCM LSI codec

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6 Author(s)
T. Nishitani ; NEC Corporation, Kawasaki, Japan ; I. Kuroda ; M. Satoh ; T. Katoh
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An LSI ADPCM codec, which is based on the CCITT standard 32 kbps algorithm, has been developed. The LSI chip has been designed as a software controllable signal processor whose architecture is optimized for the CCITT algorithm. A reconfigurable pipeline multiplier-normalizer-accumulator circuit is effectively utilized for realizing complex ADPCM specifications. The LSI chip, implemented by 2.5 µ CMOS technology, dissipates only 90 milliwatts of power.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.  (Volume:10 )

Date of Conference:

Apr 1985