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Logic synthesis for programmable gate arrays

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5 Author(s)
R. Murgai ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Y. Nishizaki ; N. Shenoy ; R. K. Brayton
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The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990