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Speed up of test generation using high-level primitives

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4 Author(s)
R. P. Kunda ; Illinois Univ., Urbana, IL, USA ; P. Narain ; J. A. Abraham ; B. D. Rathi

A general methodology to speed up the test generation process for combinational circuits with high-level primitives is proposed. The technique is able to handle circuits in a hierarchical fashion, treats the signal at a bit-vector level rather than the bit level and takes advantage of the complex operations that are available in the computer system. The technique has been implemented and the results are presented for five circuits. It is shown that by using the high-level primitives a significant speed-up and significant reduction in storage requirement are achieved. More importantly, the reduction in storage size permits test generation for very large circuits. It is clear that use of high-level primitives is more efficient than use of low-level primitives in test generation. A dependency-directed backtracking mechanism is also present which reduces the number of backtracks. The technique presented is complete, permits test vector generation for a broad class of large circuits with complex primitives, and accommodates a very general fault model

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990