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Techniques for unit-delay compiled simulation

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2 Author(s)
Maurer, P.M. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Zhicheng Wang

Two techniques for compiled unit-delay simulation have been presented. These are a PC-set (the set of potential change times) method and a parallel technique. The PC-set method analyzes a network, determines a set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on a concept of parallel fault simulation, is faster and generates less code than the PC-method, but it is less flexible. Benchmark comparisons with an interpreted event-driven simulation show a factor of four improvement for the PC-set method and a factor of ten improvement for the parallel technique

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990