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Layout compaction with attractive and repulsive constraints

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1 Author(s)
A. Onozawa ; NTT LSI Lab., Kanagawa, Japan

A one-dimensional VLSI layout compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks [expands] the spaces among the specified layout elements without causing any design rule violations. The resultant layout has less cross-talks and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990