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A new switching architecture is proposed based on the tradeoffs of modern VLSI technology-inexpensive memory and 2-dimensional layout structures. Today, it is economically feasible to preallocate buffer space individually to each virtual circuit in every node, so that "congestion" ceases to have negative effects. On the contrary, when some low-priority circuits offer more traffic than the network can carry, full utilization of the link bandwidth is achieved. In this context, the allocation of bandwidth can be done automatically and in a "fair" way, if packets are multiplexed by circularly scanning all virtual circuits and transmitting one packet from each "ready" circuit. This multiplexing algorithm equally distributes all the available link BW to all the VC's that can use it (other than equal distribution is also possible), while it also guarantees an upper bound for the total packet delay through noncongested VC's (VC's that use less than their share of BW). We present methods for hardware implementation of such fast circular scans, and propose a structure for the switching nodes of such networks, consisting of a cross-bar arrangement like a systolic array that performs merge sorting. It is ideally suited for physical layout on printed-circuit boards or with wafer-scale integration.