This paper describes the theory, design, and testing of a Viterbi processor for a digital communication system with intersymbol interference over fading time-dispersive channels. The requirement is to implement the Viterbi algorithm for a channel memory of 9 baud at a data rate of 2400 bits/s. The processor is partitioned into three subprocessors corresponding to the correlation, state metric evaluation, and state decision-making operations. For prototype evaluation, each subprocessor is being implemented as a separate chip using4-5 mum CMOS technology. The architecture, circuit design, and subsystem characterization of the correlator chip are described in some detail. The chip is required to evaluate 1024 state transition metrics in each baud interval (about 400 ns) using a pipeline architecture. Simulation and initial test results verify the correct operation of the chip with an adequate-speed safety margin. The theory of operation and architecture of the state metric chip are described. With off-chip memory for state metric storage, the state transition metrics from the correlator chip are used to determine the winning (optimal) path in the Viterbi trellis and to calculate the corresponding 16-bit state metric for each baud interval. Implementation of the third chip which is required to make a state decision regarding the bit sequence sent is presently being investigated.