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A testable design of logic circuits under highly observable condition

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2 Author(s)
W. Xiaoqing ; Dept. of Appl. Phys., Osaka Univ., Japan ; K. Kinoshita

Two methods for modifying an arbitrary CMOS combinational circuit into a testable CMOS combinational circuit, called a k-UCP circuit, are discussed. All stuck-at faults and stuck-open faults in a k-UCP circuit can be detected by a test pattern which is a combination of no more than 2(k+1) kinds of basic sequences of fixed-length k(k +1)+1 under highly observable conditions. And all single stuck-open faults in a k-UCP circuit can be located efficiently. Experimental results show that the NAND (NOR) circuit modification is better than the general circuit modification in terms of the number of additional transistors. Experimental results also show that setting a proper backtrack limit can reduce computation time greatly. From a practical point of view, the results obtained are of value for developing CMOS ASICs (application-specific integrated circuits), where hardware overhead is allowed to some extent, but a fast diagnostic procedure is required

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990