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Design of signature circuits based on weight distributions of error-correcting codes

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2 Author(s)
K. Iwasaki ; Hitachi Ltd., Tokyo, Japan ; N. Yamaguchi

Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2m). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990