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Design of integrated circuits fully testable for delay-faults and multifaults

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2 Author(s)
S. Devadas ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; K. Keutzer

It is shown how a sophisticated orchestration of combinational synthesis-for-testability approaches can result in logic-level implementations of large integrated-circuit designs that are completely robustly path-delay fault and multifault testable. For control portions of VLSI circuits, synthesis procedures that guarantee path-delay-fault or multifault testability, starting from a sum-of-products representation of a function, are used. Hierarchical composition rules are used in the synthesis of regular structures occurring in data path portions such as parity generators and arithmetic units. It is shown how test vectors for detecting all path-delay faults and multifaults can be obtained as a by-product of the synthesis process. These techniques were successfully used on circuits with over 5000 gates. Preliminary experimental results on a data encryption chip, a small microprocessor, and a speech recognition chip are presented

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990