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Theoretical and experimental studies on magnetically coupled noise in Josephson computer chip-to-card connections are described. This noise is induced by a large-amplitude high-frequency power current. An analysis of chip surface magnetic field distributions generated by connector power current is presented. In this analytical model the contributions of the return current on ground planes and the shielding current on loops between the ground connectors to the magnetic field are considered. In order to confirm the validity of this model, the field distribution in a typical layout connection system is measured by using superconducting quantum interference device detectors fabricated on the chip. The measurement results are in good agreement with the calculated values. In addition, a typical connector layout, which reduces the magnetically coupled noise, is also designed. This shows that the region where a typical Josephson circuit receives over ten-percent noise (here 0 is the magnetic flux quantum) is limited to less than about 300µm from the power connector.