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A logic simulator serves three functions: computing the output of a circuit board for a given set of input patterns, indicating faults which have been detected by a set of input patterns (tests), and predicting race conditions which may occur. Race detection is important because races prevent faults from being detected and produce unknown states during testing, causing failed boards to pass or good boards to fail. If a simulator fails to detect a race condition, the test engineer does not become aware of its effect until he observes anomalies during production testing. This paper describes a race detection technique which is quite conservative, in that it predicts potential race conditions which are ignored by commonly used "unit delay" simulators. It requires neither modeling of tolerances of components, nor the computation of delays on all parts through the board. Additionally, because the approach is based on a mathematical technique, each logic element state computed by the simulator is available as a dynamic trace printout which helps isolate the source of the race. An example is given in which a race ignored by the unit delay method is detected in a circuit where performance is adversely affected.