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This paper discusses the applications and architectural features of a sequential pattern generator designed for a general-purpose high-speed large-scale integration (LSI) test system. This system provides enhanced capabilities for testing communications-microprocessor-oriented LSI devices which require long test patterns and flexible input-output (I-O) control of individual pins. Salient features discussed are a 10 MHz random access memory with an 80-bit word size and controller capable of 100 ns subroutine calls and loops in unlimited numbers. Also, individual pin changes such as I-O states, timing, and waveform format at 10 MHz rates are de- scribed.