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Packaging Trade-Offs for an LSI-oriented Very High-Speed Computer, the HITAC M-200H

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4 Author(s)
T. Chiba ; Central Research Lab, Japan ; A. Masaki ; K. Furumaya ; S. Hososaka

Hardware technologies used and design considerations behind important design decisions in the development of the generalpurpose very high-speed computer, HITAC M-200H, are outlined. The logic and memory make extensive use of large-scale integration (LSI) technology. Trade-offs in LSI application to random logic result in the use of 416 circuit, 0.7 ns emitter-coupled logic (ECL) masterslice LSI's for most of the processor logic. The advanced cardon-board system combined with forced air cooling accommodates 70K circuits per board on the average, and permits up to 1.7 kW power dissipation per backboard, wiring channel capacities of masterslice LSI's and logic cards are optimized based on wireability studies. A signal-delay prediction and critical path-delay check system is developed to point out bad paths that will require longer than the permitted delays, prior to the actual building of the machine. These technologies give the M-200H a machine cycle time of less than 40 ns and a processor performance of more than eight million instructions per second (M!PS).

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:4 ,  Issue: 2 )